So, we were analysing a workload in geekbench where we suspected that due to physical register file limit and utilization in our qualcomm SoC mediatek one is performing better, as they were utilizing their hardware better. Now to analyse it i was tasked with creating benchmark for checking register file limit, then i found there  are a lot of microarchitecture features, so eventually i found henry wong work then travis down work then on their github link to microarchitecturometer which uses python to generate c files for ARM based target, i used it to compile it then ran on my qualcomm SoC the one released in 2025 and compared with 9400 and 9500 what i observed was the binary was able to report qualcomm ROB and Physical register numbers with some error as matched from internal hardware documentation  but on mediatek we were unable to get the nunbers as their utilisiation and hardware was never stressed by that benchmark binary, then i found bilibili com website has some videos on qualcomm and same mediatek SoCs what they had is that qualcomm SoC uses one ROB and their numbers were way more accursate then what i got from my binaries and on mediatek also tehy were able to report and they reported 2 structures instead of one conventional ROB, this is the story so far.
End goal is that i have a benchmark to compare microarchitectural aspects on my targets and competitor and extend it to compute and servers and also other goal is that i have a plugin which can work with any benchmark i run on my qualcomm targets which will give me utlisation of basic microarchitecture asp[ects like physical register file, rob, microp cache etc......so i can see more in depth